PERFORMANCE ANALYSIS OF ON CHIP INTERCONNECTS FOR ASIC DESIGN

Circuit complexity and performance have in- creased as a result of the constant reduction in semicon- ductor device feature size. Improved area, power, and speed have resulted from scaling the lateral dimensions of planar devices like MOS transistors. Current scaling patterns hurt interconnects unique properties, especially the global lines. These lengthy resistive cables now consume more electricity and have slower signal propagation times. The connection models must now take inductive effects into account for potential inclusion. Due to these factors, precise interconnect models for on-chip devices are necessary to ascertain the signal properties and construction specifications of fast DSM interconnect. The purpose of this project is to enlighten on the difficulty in designing on-chip connections, particularly for extremely fast purposes.