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Stream/Area:
-
Subject:
-
Paper ID:
IJSREM67420
Volume:
10 |
9 |
Sep 2026
Pages:
1-6
Publication Frequency:
Monthly (12 issues per year)
License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.
Department of Electrical and Electronics Engineering,
Guru Jambheshwar University of Science and Technology, Hisar 125001, India
Department of Electrical and Electronics Engineering,
Guru Jambheshwar University of Science and Technology, Hisar 125001, India
2Department of Computer Science and Engineering
Guru Jambheshwar University of Science and Technology, Hisar 125001, India
3Dept. of Electronics and Communication Engineering
JB Institute of Technology, Dehradun, UK, India, 248197
Department of Electrical and Electronics Engineering,
Guru Jambheshwar University of Science and Technology, Hisar 125001, India
A battery management system (BMS) estimator has been designed and analyzed on the Avnet ZedBoard (Zynq-7000 XC7Z020-CLG484-1). The starting point was a neuro-fuzzy and regression method, which we proceed into fixed-point programmable logic. The evolved design has three parts: a 5–11–11–1 artificial neural network (ANN) that approximates specific gravity, a 5×7 fuzzy rule engine that classed as state of charge (SoC), and a Q16.16 multivariate regression datapath that estimates used and expected life. Verification is split into four levels so that floating-point model behavior, quantization effects, RTL behavior, and on-board execution can be scrutinized disparately. We then instrumented the design in Vivado 2019.2 at target clock frequencies between 15 and 100 MHz. At 100 MHz the worst negative slack (WNS) is −9.564 ns, which puts the critical-path delay at about 19.564 ns, nearly twice the 10-ns period. At 50 MHz the WNS shrinks to −0.073 ns, still a failure, and the first positive margin appears at 45.455 MHz (WNS = 0.475 ns). Total on-chip power falls only slightly across the sweep, from 1.698 W at 100 MHz to 1.671 W at 15 MHz, and the DSP, flip-flop, and LUTRAM counts do not change. For the present non pipelined design, roughly 45 MHz is therefore the highest frequency at which timing closure has been shown perfect; going faster will need the critical path to be restructured or pipelined.
KEYWORDS
This study expressed and evaluated the performance for an intelligent BMS estimator on a Zynq-7000 FPGA. The complete model is paired a fixed-point 5–11–11–1 ANN algorithm for a specific-gravity (SG) estimation with a SoC engine with fuzzy 35-rule and in the end a regression block predict expected battery life. The results expressed mainly for a controlled frequency sweep simulation and synthesis. The obtained results shows that timing closure fails at 100 MHz and 50 MHz (WNS = −9.564 & −0.073 ns). The highest operating point that meets the timing is 45.455 MHz with WNS = 0.475 ns, and 40 MHz provides a large margin of 3.475 ns. The total on-chip power decrease a little as the frequency starts elevating down, and the utilization for resource moves a little bit: six DSP blocks, 60 LUTRAMs, and 945 flip-flops at every point.
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Publication Date
9/23/2026
Peer Review Type
Double-Blind Peer Review
Review Rounds: 2
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