Power and Area Optimized Logically Obfuscated n-bit ALU Using Majority Gate Logic for Enhanced Hardware Security

With the increasing vulnerability of integrated circuits to hardware attacks such as reverse engineering and intellectual property theft, incorporating security at the architectural level has become essential in VLSI design. This paper presents a power and area optimized logically obfuscated n-bit Arithmetic Logic Unit (ALU) aimed at enhancing hardware security. The proposed design integrates encryption logic directly into the full adder architecture, where the full adder is implemented using majority-gate-based logic combined with key-controlled obfuscation. Correct functionality of the ALU is achieved only when the valid encryption key (K1K0 = 01) is applied, thereby preventing unauthorized use and analysis. The use of majority gates enables compact realization of arithmetic operations with reduced switching activity, contributing to lower power consumption and area overhead. A Karatsuba multiplier replaces the conventional Vedic multiplier to reduce computational complexity from O(n²) to O(n¹·⁵⁸). The complete ALU is described in Verilog HDL and synthesized on a Xilinx Vivado FPGA platform. Synthesis results demonstrate that the proposed design achieves enhanced resistance to reverse engineering attacks with marginal increases in power (5.2%) and silicon area (6.8%) compared to a conventional ALU, making it suitable for secure processors and resource-constrained embedded systems.