Power – Efficient FPGA Implementation of Retinex – Based Low-Light Image Enhancement Using Flip-Flop Clock Gating

Low-light image enhancement is an essential task in modern image processing applications such as surveillance, autonomous vehicles, and medical imaging. Retinex-based algorithms are widely used due to their ability to simulate human visual perception by separating illumination and reflectance components. However, their hardware implementation is complex and power-consuming. This paper proposes a power-efficient FPGA implementation of a Retinex-based low-light image enhancement system using flip-flop-based clock gating. The proposed approach incorporates an edge-preserving filter for efficient illumination estimation and reduces computational complexity through hardware optimization. Clock gating minimizes unnecessary switching activity, significantly reducing power consumption. Experimental results demonstrate that the proposed system achieves substantial power reduction while maintaining image quality and real-time performance.