Realization of an All-Digital Phase-Locked Loop

Realization of an All-Digital Phase-Locked Loop

Mrs. Shyamala S C1, Latish Patil2, Srinivas Gowda K R3, Yashwanth T4 , Dhruva Kumar T R5

1Proffessor,2Final year Student, 3Final year Student, 4Final year Student,5Final year Student

Department of Electronics and Communication Engineering

P E S Institute of Technology and Management, Shivamogga

Abstract - An all-digital phase locked loop (PLL) is  presented in the paper. The goal of a PLL, a closed-loop control system, is to synchronize the phase and frequency of an incoming signal. Clock generation and recovery  communication systems are the most flexible uses of PLL.
Digital PLLs are chosen because of the greater integration of digital designs. The implementation of ADPLL utilizing a Xilinx Vivado tool and code is written in Verilog.

Key Words:  All Digital PLL, digitally controlled oscillator(DCO),Low Pass Filter(LPF),Increment-Decrement (ID)