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Stream/Area:
-
Subject:
-
Paper ID:
10.55041/IJSREM39448
Volume:
8 |
12 |
Dec 2024
Pages:
Publication Frequency:
Monthly (12 issues per year)
License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.
An all-digital phase locked loop (PLL) is presented in the paper. The goal of a PLL, a closed-loop control system, is to synchronize the phase and frequency of an incoming signal. Clock generation and recovery communication systems are the most flexible uses of PLL. Digital PLLs are chosen because of the greater integration of digital designs. The implementation of ADPLL utilizing a Xilinx Vivado tool and code is written in Verilog.
KEYWORDS
Publication Date
4/11/2024
Peer Review Type
Double-Blind Peer Review
Review Rounds: 2
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Conflict of Interest
The authors declare no conflict of interest related to this research work.
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