SAPON-Based Offset-Canceling Tri-State Sensing Latch for High- Precision and Power-Efficient NAND Flash Memory Applications

Through the integration of the tristate sensing latch with the Offset Canceling Sensing Latch (OCSL), significant changes occur in the sense phase, rendering it independent from the inverter PMOS. This modification notably eliminates the inherent voltage variation in the trip point caused by the inverter PMOS. Additionally, incorporating the tristate sensing latch eliminates short-circuit currents during read operations, leading to a substantial decrease in energy consumption during both sample and sense phases. Furthermore, the absence of short-circuit currents in read operations mitigates the risk of data corruption in the sensing latch during the sample phase. Overall, this enhancement in the sensing latch mechanism enhances stability, reduces energy consumption, and improves data integrity during the sample phase, thus contributing to a reduction in power consumption and delay through the SAPON Approach.

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