Simulation And Analysis of Inverting and Non-Inverting Mixed-Logic 2×4 Decoders Using 32NM Finfet Technology

This Project introduces the need for higher performance applications with low power consumption as we see there is lots of difficulty in using low power devices for a higher rank application like microprocessor, DSP, SRAM. As we know the Decoder plays an important role in memory design & logical circuit design. In this Project, we have been comparing the parameter Power delay product, Energy delay product, Power consumption, and Delay on 12T, 14T decoder base on MOS, FinFET, and FinFET using CMOS as proposed in 32nm technology. So the final proposed circuit is obtained by application of FinFET, to vary threshold from the ground path of the final 12T. Where we get significant improvement in proposed work.