Simulation And Analysis of Inverting and Non-Inverting Mixed-Logic 2×4 Decoders Using 32NM Finfet Technology

Simulation And Analysis of Inverting and Non-Inverting Mixed-Logic 2x4 Decoders Using 32NM Finfet Technology

1Ms.B.Jyothsna  2Manasa Bonagiri  3Anusha Ranga 4Ashwini Dhukire

1Associate Professor, Electronics and Communication Engineering, Bhoj Reddy Engineering College For Women

2,3,4B.Tech Students , Electronics and Communication Engineering, Bhoj Reddy Engineering College For Women

ABSTRACT

This Project introduces the need for higher performance applications with low power consumption as we see there is lots of difficulty in using low power devices for a higher rank application like microprocessor, DSP, SRAM. As we know the Decoder plays an important role in memory design & logical circuit design. In this Project, we have been comparing the parameter Power delay product, Energy delay product, Power consumption, and Delay on 12T, 14T decoder base on MOS, FinFET, and FinFET using CMOS as proposed in 32nm technology. So the final proposed circuit is obtained by application of FinFET, to vary threshold from the ground path of the final 12T. Where we get significant improvement in proposed work.

KEYWORDS: High Delay, High Performance, 45nm Technology, FinFET 32nm Technology low power.