Simulation of an approximate Discrete Cosine Transform architecture using Verilog

This paper presents the simulation and implementation of an approximate Discrete Cosine Transform (DCT) architecture using Verilog for image compression applications. DCT, a key component in standards such as JPEG, transforms spatial data into frequency components to reduce redundancy. To address the high hardware complexity of conventional designs, the proposed architecture replaces multipliers with adders, subtractors, shift operations, and a clock gating technique, significantly reducing area and power consumption. The algorithm is initially validated in MATLAB R2020a and subsequently implemented on an FPGA using Xilinx Vivado targeting an Artix-7 XC7VX330T device. Experimental results demonstrate that the design achieves lower hardware complexity, improved processing efficiency, and reduced power usage, making it well-suited for real-time image compression systems.