Single Ended 6T Static RAM with Tri Gate FinFET in Shorted Gate Mode

The decision to maximize performance in terms of overall performance, power consumption, delay, leakage, and time to market (opportunity cost) has not changed since the advent of the integrated circuit (IC) industry. In fact, Moore’s law is all about optimizing those parameters to their fullest potential. However, while scaling of producing nodes continued in the direction of below 32 nm, certain of the tool settings could not be scaled any further, most notably the power supply voltage, which is the primary component in determining dynamic electricity. This was the case even though scaling of producing nodes continued in the direction of below 32 nm. Through the course of this research, the power consumption, latency, and leakage currents in 6T SRAM cells are all going to be reduced. When looking at the power consumption and delay of SRAM, the backend device Synopsys HSPICE was used for the experiment. Using FINFET technology, this study builds and simulates a 6T SRAM in a 32 nm era. The size of the device is measured in nanometers.