Subthreshold Leakage Current Reduction Technique in Large Scale Integration with SRAM

Subthreshold Leakage Current Reduction Technique in Large Scale Integration with SRAM

Prof. Dipangi Nayak¹, Prof. Suresh S. Gawande²

¹Professor, Department of Electronics and Communication Engineering, BERI, Bhopal, India

     ²Professor, Department of Electronics and Communication Engineering, BERI, Bhopal, India

Abstract - Static power dissipation is due to leakage current when the transistor is normally off. The two main sources of power dissipation in CMOS circuits are static and dynamic power dissipation. By scaling down the feature size the dynamic power dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power dissipation. So, in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage current has become a challenging area for VLSI chip designers. Leakage current occurs in both active and standby modes. Gate leakage, subthreshold leakage cannot be solved by MOS structures nor by introducing new material. One of the feasible solutions is by combinational use of Low- Vt transistors for its high-speed capability and High- Vt transistors for very small leakage current. Multi-Threshold CMOS(MTCMOS) and Variable-Threshold CMOS (VTCMOS) are biasing techniques that uses combinations of different threshold voltage and are suitable for SRAM design.

Keywords: leakage power, CMOS, VTCMOS, Feature size, Subthreshold,