Synthesis and Performance Characterization of a Pipelined 32-Bit Vedic Multiplier for High-Speed Digital Systems

This paper introduces a high speed, area and power efficient approximation method for 32 bit arithmetic operations with a Vedic multiplier and parallel prefix adder (PPA). Vedic multiplication methods are highly recognized for their high-speed calculations, while parallel prefix adders offer lower latency in addition. By combining both methods, we introduced an optimized hardware architecture that offers lower area overhead without compromising computational efficiency. The proposed 32- bit arithmetic unit employing the Urdhva-Tiryagbhyam technique, multiplication is executed with reduced delay, while the PPA significantly enhances addition by minimizing carry propagation time. The given design is synthesized and compared in terms of area, delay, and power.