VLSI-optimized Two-Bit Error Detection and One-Bit Error Correction for Enhanced Data Integrity

VLSI-optimized Two-Bit Error Detection and One-Bit Error Correction for Enhanced Data Integrity

Dr.R.K.Navandar1, Kalyani Awatade2, Gauri Ghadi3, Poonam Gaikwad4

1Dr. R. K. Navandar, Dept. Of ENTC, JSPM’s JSCOE, Pune, Maharashtra, India

2Kalyani Awatade , Dept. Of ENTC, JSPM’s JSCOE, Pune, Maharashtra, India

3Gauri Ghadi ,  Dept. Of ENTC, JSPM’s JSCOE, Pune, Maharashtra, India

3Poonam Gaikwad , Dept. Of ENTC, JSPM’s JSCOE, Pune, Maharashtra, India

Abstract : This project presents a new VLSI-optimized solution for enhancing data integrity through 2-bit error detection and 1-bit error correction. It consist some limitations in existing approaches our project aimed to advance the field by introducing an efficient algorithm in Very Large Scale Integration (VLSI) system. We have worked on studying the reason that causes errors in digital transmission process and receiving of data and developed a code in Very High Speed Integrated Circuit Hardware Descriptive Language (VHDL) that optimizes error detection and correction processes, addressing challenges in contemporary data storage and communication systems.
Xilinx ISE Design Suite 14.7 was used for performing the implementation of the code and observing the relevant output in order to know where the error bit was. Our project aimed to detect upto 2 bits and correct 1 bit. Simulation results demonstrated that the proposed approach is capable of achieving high reliability digital systems such as flight critical systems in airplanes, space shuttles, and missile electronics systems.

Key Words:  Error detection, error correction, VLSI, digital systems, data storage.