Wireless Communication Between Multi-FPGAs

PHY Layer implementation of the IEEE 802.11 a/g/n Wi-Fi standard using Software-Defined Radio (SDR) architecture. It addresses the challenge of implementing Wi-Fi on SDR platforms, which has been difficult due to the strict timing requirements of Wi-Fi protocols such as the Short Inter-Frame Space (SIFS) and the need for low-latency communication between the radio front-end and the processing unit. This architecture enables the implementation of the PHY (Physical layer) and low-level MAC (Media Access Control) functionalities in the FPGA, ensuring low latency and precise timing control.