Crossref DOIMemberCiteFactoropen accessissn
SJIF Impact Factor 8.659 | ISSN: 2582-3930
IJSREM Logo

International Journal of Scientific Research in Engineering and Management

(Gateway to Global Scholars - An International, Scholarly, Multi-Disciplinary, Open Access Journal)

Peer-Reviewed Journal Designed to Meet UGC's Quality Parameters

HomeCurrent IssuePast IssuesPay OnlineConferencesEditorial BoardAbout UsContact Us
IJSREM

Loading article...

Follow Us

  • Google Scholar
  • ResearchGate
  • Academia.edu
  • Mendeley
  • LinkedIn
  • Facebook
  • Instagram

Journal Policies

  • Peer Review Policy
  • Publication Ethics
  • Copyright Infringement
  • Refund & Cancellation Policy
  • Terms and Conditions
  • Privacy Policy

Journal Identifiers & Licenses

  • ISSN Verified: 2582-3930ISSN Verified: 2582-3930
  • Crossref DOI: 10.55041Crossref DOI: 10.55041
  • SJIF Ranking: 08.659SJIF Ranking: 08.659
  • Licensed under CC BY 4.0Licensed under CC BY 4.0
  • ISO Certification: 9001:2015ISO Certification: 9001:2015
  • Indexed & Cited In: Google ScholarIndexed & Cited In: Google Scholar

Contact Us

International Journal of Scientific Research in Engineering and Management (IJSREM)

#62/1, New No 7, 1st Cross, 2nd Main, Ganganagar, R T Nagar, Bangalore North, Bangalore, Karnataka, India – 560032
[email protected]+91 93911 67991
logos
logos
Working Hours

Mon – Sat: 9:00 AM – 6:00 PM

Sunday: 10:00 AM – 4:00 PM

+91 93911 67991

© 2026 IJSREM – International Journal of Scientific Research in Engineering and Management. This is an open-access journal. Articles are published under the Creative Commons Attribution (CC BY 4.0) License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

DisclaimerPrivacy PolicyTerms and Conditions
ArticlePeer ReviewedOpen AccessPlagiarism Passed
Paper ID:IJSREM66302

A Systematic Review of Hybrid AI Frameworks Combining Circuit-Level Optimization and Machine Learning Approaches

Stream/Area:

-

Subject:

-

Paper ID:

IJSREM66302

Volume:

10 |

7 |

Jul 2026

Pages:

1-22

Publication Frequency:

Monthly (12 issues per year)

DOI
Digital Object Identifier
Not assigned

License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.

Share this article:

Authors

UBP

Umesh Balkishan Phiske

Department of Civil Engineering

Electronics and Telecommunication Department, ALARD School of Interdisciplinary Research, ALARD University

Download Author Certificate

Mentors

DGDD

Dr. Goplakrishna D. Dalvi

HOD, Electronics and Telecommunication Department,

ALARD School of Interdisciplinary Research, ALARD University, Pune

Download Mentor Certificate

Author Services & Downloads

Full ArticlesAcceptance Certificate

Abstract

This study presents a comprehensive systematic review of Hybrid Artificial Intelligence (AI) frameworks that integrate circuit-level optimization with machine learning (ML), reinforcement learning (RL), and evolutionary algorithms. By analyzing bibliometric data and technical literature from 2015–2025, the paper synthesizes how AI-driven approaches revolutionize Very Large-Scale Integration (VLSI) and hardware design automation. The review identifies key trends in AI-integrated Electronic Design Automation (EDA), emphasizing hybrid models that achieve superior trade-offs in power, performance, and area (PPA). Reinforcement learning and genetic algorithms enable global optimization, while deep learning methods enhance prediction accuracy and scalability. The findings demonstrate significant performance improvements reducing design time and computational cost—compared to traditional rule-based systems. However, challenges persist in interpretability, real-time adaptability, and integration overhead. The study provides a structured taxonomy of hybrid AI systems, evaluates their methodological strengths, and highlights research gaps in scalability and explainability. Overall, it contributes a unified perspective and roadmap for future intelligent hardware co-design.

KEYWORDS

Hybrid AI Circuit-Level Optimization Machine Learning Reinforcement Learning VLSI Design Hardware Co-Design

Cite This Article

Umesh Balkishan Phiske, Dr. Goplakrishna D. Dalvi, "A Systematic Review of Hybrid AI Frameworks Combining Circuit-Level Optimization and Machine Learning Approaches," International Journal of Scientific Research in Engineering and Management, vol. 10, no. 7, pp. 1-22, Jul 2026.

Full Article/Conclusion

This review focused on the integration of evolutionary, learning, and reinforcement techniques with circuit-level optimisation. The analysis indicated that hybrid AI excelled in adapting automation, fast convergence, and design flexibility beyond traditional heuristics and deterministic models. The bibliometrics showed a prominent and unrivalled rise in the design of intelligent hardware from 2015-2025 by Tsinghua University, the University of Chinese Academy of Sciences, and Harvard University, illustrating perceptible international cooperation in the field. The advancement of hybrid AI enabled self-predictive and adaptive learning electronic systems in FPGA optimisation, quantum circuit design, and neuromorphic architecture. With these hybrid systems, the models transition from a hardware design process of parameter tuning to one driven by data. The review provides significant contributions to the field by offering a hybrid AI systems taxonomy and synthesis while outlining the need for adaptively, real-time explainability, and lightweight models. Further work is also recommended for the development of AI-integrated EDA tools for automated circuit design. Overall, this study outlines the first comprehensive vision on hybrid AI–hardware co-design by marrying intelligent computation with engineering design for the development of smart, energy-efficient electronics.

References

1.      Agnesina, A., et al. (2020). VLSI Placement Parameter Optimization using Deep Reinforcement Learning. ICCAD paper / technical report. Retrieved from https://www.gtcad.gatech.edu/www/papers/agnesina-iccad20.pdf. gtcad.gatech.edu 2.      Attaoui, Y., Chentouf, M., & Ismaili, Z. E. A. (2024). Machine Learning in VLSI Design: A Comprehensive Review. Journal of Integrated Circuits and Systems. Retrieved from https://jics.org.br/ojs/index.php/JICS/article/download/826/500. jics.org.br+1 3.      Fernando, P. R. (2019). Genetic Algorithm Based Design and Optimization of VLSI. University/Technical Report. Retrieved from https://digitalcommons.usf.edu/cgi/viewcontent.cgi?article=2962&context=etd. digitalcommons.usf.edu 4.      Wang, Z. (2024). A Review on FPGA-Based Optimization and Applications of CNNs. CEUR Workshops. Retrieved from https://ceur-ws.org/Vol-3748/paper13.pdf. ceur-ws.org 5.      Karuppasamy, K., Puram, V., Johnson, S., & Thomas, J. P. (2024). A Comprehensive Review of Quantum Circuit Optimization: Current Trends and Future Directions. arXiv. Retrieved from https://arxiv.org/pdf/2408.08941. arXiv 6.      Paler, A. (2023). Machine Learning Optimization of Quantum Circuit Layouts. ACM Proceedings. Retrieved from https://dl.acm.org/doi/10.1145/3565271. dl.acm.org 7.      Riu, J., et al. (2025). Reinforcement Learning Based Quantum Circuit Optimization (ZX-diagram RL + GNNs). Quantum Journal. Retrieved from https://quantum-journal.org/papers/q-2025-05-28-1758/. Quantum 8.      “Machine Learning in VLSI layout design” (2024). Leveraging ML for enhanced automation in VLSI layout design. Journal/Report. Retrieved from https://urfjournals.org/open-access/leveraging-machine-learning-for-enhanced-automation-in-vlsi-layout-design-optimizing-performance-and-efficiency.pdf. urfjournals.org 9.      Research on FPGA ML accelerators (survey) — Darvish Rouhani, et al. (2024). A survey on FPGA-based accelerators for ML models. arXiv. Retrieved from https://arxiv.org/html/2412.15666v1. arXiv 10.   “Deep RL Global Router” — Enhanced DRL routing (2023). An Enhanced Deep Reinforcement Learning-Based Global Router for VLSI Design. Retrieved from https://www.researchgate.net/publication/370564725_An_Enhanced_Deep_Reinforcement_Learning-Based_Global_Router_for_VLSI_Design

Editorial & Review Transparency

Publication Date

7/25/2026

Peer Review Type

Double-Blind Peer Review

Review Rounds: 2

Documents

Review Report (Confidential)
Copyright Form (Office)

Article Metrics & Impact

Article Views

3

Total views since publication

PDF Downloads

12

Total downloads since publication

Geographic Reach

5

Indexing, Archiving & Preservation

Google Scholar
Academia
ResearchGate
Crossref
SSRN
Semantic Scholar
Thomson Reuters
WorldCat
Mendeley
OpenAlex
EBSCO
Zenodo

Digital Preservation: This article is permanently archived on Zenodo and complies with all data preservation standards across major indexing platforms.

Ethics, Compliance & Transparency

Plagiarism Screening

This manuscript has been checked for plagiarism using TurnitinPlagiarismChecker software.

Conflict of Interest

The authors declare no conflict of interest related to this research work.

Funding Information

No funding information available for this research.

Similar & Recommended Articles

Similar Articles by Topic

Related research in the same subject area

Loading similar articles...