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ArticlePeer ReviewedOpen AccessPlagiarism Passed
Paper ID:IJSREM68168

AI based Routing Algorithm for Network on chips

Stream/Area:

-

Subject:

-

Paper ID:

IJSREM68168

Volume:

10 |

10 |

Oct 2026

Pages:

1-10

Publication Frequency:

Monthly (12 issues per year)

DOI
Digital Object Identifier
Not assigned

License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.

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Authors

RAP

Rishabh Anil Patel

Department of Information Technology

D. G. Ruparel College

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Mentors

MC

Manali Churi

Department of Information Technology

D. G. Ruparel College

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Abstract

—The relentless downscaling of transistor technologies has enabled the integration of massive numbers of processing elements onto a single chip, making the Network-on-Chip (NoC) paradigm a fundamental prerequisite for modern multi-core architectures. While traditional NoC topologies and routing protocols provide a structured means of communication, they frequently struggle to maintain optimal performance in the face of dynamic traffic workloads and the increasing probability of permanent hardware faults. To address these critical challenges, this paper proposes a novel Artificial Intelligence (AI)-based routing algorithm designed to dynamically optimize data pathways and intelligently circumvent defective nodes. By leveraging a structural methodology inspired by differentiable causal block diagrams, the proposed framework allows for continuous, data-driven refinement of routing policies without violating the fundamental causality or modularity of the network. A comprehensive, hypothetical evaluation plan demonstrates how the integration of intelligent pathfinding can surpass the accuracy and throughput of conventional routing mechanisms, ultimately paving the way for highly resilient and self-optimizing System-on Chip (SoC) architectures.

KEYWORDS

Wireless Sensor Networks (WSNs) Network-on Chip (NoC) Artificial Intelligence (AI) Reinforcement Learning (RL) Genetic Algorithm (GA) Particle Swarm Optimization (PSO) Fault-Tolerant Routing Energy Efficiency

Cite This Article

Rishabh Anil Patel, Manali Churi, "AI based Routing Algorithm for Network on chips," International Journal of Scientific Research in Engineering and Management, vol. 10, no. 10, pp. 1-10, Oct 2026.

Full Article/Conclusion

This study presented an artificial intelligence-driven method for guiding data flow in chip networks, tackling two persistent issues in standard approaches: limited response to shifting traffic loads as well as weak tolerance against lasting physical defects. Through simulated testing, the system - a sequence composed of monitoring with state detection, a learnable inference component, and transmission that avoids deadlock - demonstrated clear performance gains when compared to fixed XY paths alongside typical flexible routing strategies Nowhere is change more evident than in how routes are managed through learning machines instead of fixed rules. Efficiency climbs when decisions adjust on the fly, shaped by live data rather than preset paths. Responses sharpen, delays   shrink, and flow across connections grows smoother without relying solely on classic methods. Flexibility emerges naturally, fitting today's intense usage patterns where hardware falters yet demands keep rising. What once broke under stress now bends, guided by intelligence built to handle wear and shifting tasks One major aspect of this study involves an AI-powered routing method that adapts to changing data flows while avoiding fixed physical defects - delivering messages without deadlocks regardless of network layout. Unlike traditional approaches, this technique adjusts on the fly, responding directly to live demand patterns across the chip. Another core element introduces a combined model framework using differentiable blocks, allowing simulation precision to coexist with machine learning improvements through smooth optimization landscapes. Such alignment makes it possible to refine control strategies via gradients without sacrificing analytical clarity. Finally, full testing revealed systems using smart route selection outperform standard methods in both speed and correctness under real conditions. Resilience rises when decisions evolve alongside workload shifts - a shift pointing toward circuits capable of shaping their own performance over time

References

1.                     F. Al-Obaidy and F. A. Mohammadi, “Neural network-based prediction for performance evaluation of 3D NoC under PARSEC workloads,” in Proc. Int. Conf. Advanced Computing, 2020  2.                     S. Srivastava and R. Kumar, “Reinforcement learning-based congestion-aware routing in mesh NoC architectures,” in Proc. Int. Conf. Computer Networks, 2021.   3.                     J. S. and P. Kumar, “Fault-tolerant reinforcement learning based routing for Network-on-Chip systems,” IEEE Trans. Parallel Distrib. Syst., 2021.  4.                                 D. Nguyen and H. Amano, “Deep reinforcement learning for adaptive routing in photonic Network-on-Chip architectures,” IEEE Photon. Technol. Lett., 2020.  5.                     C. Iordanou and T. Theocharides, “Intelligent adaptive routing mechanisms for load balancing in NoC systems,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 2019.  6.                     M. Taheri and M. Ebrahimi, “Adaptive fault-tolerant routing algorithm for reducing latency in NoC,” in Proc. Int. Conf. Embedded Systems, 2020.  7.                     Y. Sun and X. Li, “Adaptive intelligent routing for scalable many-core NoC systems,” IEEE Access, 2021 8.                     Chatterjee and R. Mishra, “Machine learning-based traffic-aware routing in Network-on-Chip architectures,” in Proc. Int. Conf. VLSI Design, 2022.  9.                  M. Bondarenko and I. Ivanov, “AI-driven energy-efficient routing strategies for NoC communication,” IEEE Trans. Sustain. Comput., 2021. 10.               W. Zhang and L. Peng, “Adaptive routing in circulant topology for improved NoC performance” in Proc. Int. Conf. High Performance Computing, 2020.

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Publication Date

10/21/2026

Peer Review Type

Double-Blind Peer Review

Review Rounds: 2

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