DESIGN AND COMPARATIVE ANALYSIS of A MODIFIED PERFORMANCE OPTIMIZED BBL-PT FULL ADDER IN 90nm CMOS TECHNOLOGY

This work presented the design and comparative analysis of three modified BBL-PT based full adder architectures implemented using 90 nm CMOS technology. The study began by analyzing existing full adder designs, including Conventional CMOS, Complementary Pass Logic (CPL), the BBL-PT full adder, and the Hybrid LP XOR/XNOR full adder. Although these architectures offer improvements in specific performance metrics, the conventional BBL-PT full adder suffers from a voltage stepping problem in the PTL-based sum block due to the PMOS restorer, while the Hybrid LP XOR/XNOR design increases transistor count and circuit complexity. These limitations motivated the development of modified BBL-PT architectures capable of achieving a better balance between power consumption, propagation delay, transistor count, and signal integrity. To address these challenges, three modified full adder architectures were proposed with different optimization objectives. The first design improves voltage stability by incorporating a current-source-assisted sum block, the second design employs optimized hybrid logic with separate sum and carry paths to reduce the critical path delay, and the third design utilizes a compact hybrid pass transistor structure to minimize transistor count and switching capacitance. Simulation results obtained using Cadence Virtuoso demonstrate that all three proposed designs successfully eliminate the voltage stepping issue and improve the overall performance of the full adder. Among them, Proposed Design–2 achieves the best overall Power-Delay Product (PDP) and propagation delay, whereas Proposed Design–3 offers the lowest transistor count and power consumption. These results indicate that the proposed architectures are promising candidates for energy-efficient and high-speed arithmetic circuits in modern VLSI systems.

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