DESIGN AND IMPLEMENTATION OF NOVEL ADDER AND MULTIPLIER IMAGE ENHANCEMENT APPLICATION

  In this paper, a novel adder and multiplier design for image enhancement applications has been successfully implemented. The proposed system addresses the limitations of conventional arithmetic circuits by reducing propagation delay and power consumption.   The improved performance of arithmetic operations directly enhances image processing efficiency and output quality. The system is suitable for real-time applications due to its high speed and optimized design.   Overall, the project demonstrates that efficient arithmetic architectures can significantly improve the performance of digital image processing systems.

[1] S. Knowles, “A Family of Adders,” Proc. IEEE Symposium on Computer Arithmetic, 2001.   [2]R. P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders,” IEEE Trans. Computers, 1982.   [3]C. S. Wallace, “A Suggestion for a Fast Multiplier,” IEEE Trans. Electronic Computers, 1964.   [4] R. C. Gonzalez and R. E. Woods, Digital Image Processing, Pearson, 2008.   [5]K. K. Parhi, VLSI Digital Signal Processing Systems, Wiley, 1999.   [6]N. H. E. Weste and D. Harris, CMOS VLSI Design, Pearson, 2011.   [7]S. Vadlamudi et al., “Enhancing Image Processing Using Approximate Multipliers,” IJCESEN, 2024.   [8] T. Mendez and M. Badiger, “Power-Efficient Multipliers for Image Sharpening,” ETASR, 2025.   [9] M. B. R. Srinivas et al., “Optimized Approximate Multiplier for Image Applications,” Scientific Reports, 2025.   [10]“Efficient Approximate Multipliers for Image Processing,” Microprocessors and Microsystems, 2023.