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Paper ID:IJSREM68527

Design and Performance Analysis of a Reduced-Capacitance H-9 Five-Level Switched-Boost Capacitor Transformer less Inverter

Stream/Area:

-

Subject:

-

Paper ID:

IJSREM68527

Volume:

10 |

10 |

Oct 2026

Pages:

1-5

Publication Frequency:

Monthly (12 issues per year)

DOI
Digital Object Identifier
10.55041/IJSREM68527

License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.

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Authors

GA

G. Aruna

Elecrical and Electronics Engineering

Holy Mary Institute of Technology and Science

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C

CH.Rajasri

Elecrical and Electronics Engineering

Holy Mary Institute of Technology and Science

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TR

T. Rajeswari

Elecrical and Electronics Engineering

Holy Mary Institute of Technology and Science

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Abstract

This paper examines a single-stage, single-phase H-9 transformerless inverter integrating a switched-boost (SB) cell, switched-capacitor (SC) network and polarity-generation bridge for photovoltaic energy conversion. The architecture uses nine semiconductor switches and synthesizes five output levels while reducing the need for large energy-storage capacitors. The study reorganizes the supplied design documentation, switching relations, Simulink plots and reported experimental observations. For a 40 V input and a duty ratio of 0.6, the ideal capacitor voltage is 100 V and the maximum pole-voltage magnitude is 200 V. The supplied documentation reports leakage currents of 10 mA and 12.8 mA at 50 and 30 ohm loads, respectively, and a filtered-voltage THD of 1.29% in a cited prototype study. Source simulation traces are reproduced and distinguished from those experimental reports. Practical limitations, including capacitor startup transients and grid-interface verification, are discussed.

KEYWORDS

H-9 inverter five-level conversion photovoltaic switched boost switched capacitor leakage current transformer-less inverter.

Cite This Article

G. Aruna, CH.Rajasri, T. Rajeswari, "Design and Performance Analysis of a Reduced-Capacitance H-9 Five-Level Switched-Boost Capacitor Transformer less Inverter," International Journal of Scientific Research in Engineering and Management, vol. 10, no. 10, pp. 1-5, Oct 2026. https://doi.org/10.55041/IJSREM68527

Full Article/Conclusion

A seven-page technical synthesis of the reduced-capacitance H-9 five-level switched-boost capacitor transformer-less inverter has been presented using the uploaded Aruna documentation. The ideal voltage relations predict a 100 V switched-capacitor voltage and ±200 V peak level at 40 V input and D = 0.6. The supplied simulation figures illustrate input-voltage regulation, current startup, ac waveforms and capacitor behavior. Separately, source-reported prototype measurements describe low leakage currents and 1.29% filtered-voltage THD. Reproduction of these experimental claims requires the original circuit files, control implementation and measurement records.

References

[1]  Aruna,  “A  H-9  Five-Level  Switched  Boost  Capacitor Transformer-less Inverter with Lower Capacitance,” [2] “An inductorless triple-boost 13-level switched-capacitor inverter with reduced ripple current,” [3] “A novel active neutral-point-clamped five-level inverter with single-stage integrated dynamic voltage boosting. [4] “Common-ground type inverter with dynamic boosting and reactive compensation for grid,” [5] “A new family of single-phase five-level transformer less inverters for solar PV applications,” [6] “A quasi-switched-capacitor-based grid-connected PV inverter with minimum leakage current

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Publication Date

10/30/2026

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Double-Blind Peer Review

Review Rounds: 2

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