Design and Simulation of a BCD Up-Down Counter Using VLSI

A 4‑bit BCD Up‑Down counter and its 8‑bit two‑digit version were designed in Verilog HDL and checked using AMD Vivado Design Suite. I built the 4‑bit counter. The 4‑bit counter counts in both directions while the 8‑bit version uses two connected stages to represent two decimal digits. Simulation was used to check reset, direction control, decimal rollover and clocked state updates. In the two‑digit design. Borrow conditions transfer the count between the units and tens stages. The RTL synthesis view provides a view of the logic described in HDL. Overall the project demonstrates how a small BCD counter can be built, tested and reused as a module for a decimal counter. A key advantage of this approach is that the same 4‑bit block can be reused of writing a separate counter for every digit. Once the basic stage is tested additional digits can be added using the counting method. Design makes the design a useful exercise, in logic Verilog HDL, simulation and FPGA‑oriented synthesis.

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