Design of a Ternary Segmented MUX-Based Approximate Adder for Low-power Applications

The study developed an approximate adder which uses a ternary segmented MUX structure to enable dynamic accuracy changes between two different operational modes, which results in better power consumption and faster processing speeds for applications that tolerate errors. The proposed architecture divides the adder into an approximate LSB region and an accurate MSB region, separated by a dynamic ternary boundary half-adder. The design achieves reduced switching activity and critical path delay through lower significant bit approximation together with 3:1 MUX-based ternary logic, which maintains higher-order accuracy. The results from the Xilinx Vivado implementation show a 15.45% decrease in total on-chip power consumption, dropping from 10.125 W to 8.56 W. Additionally, the critical path delay is reduced by 5.35%, from 8.607 ns to 8.146 ns. The system operates at its maximum frequency of 122.7 MHz while maintaining a junction temperature of 41.1°C which demonstrates better thermal efficiency. The research can progress through multiple paths for future work. The proposed architecture can be realized through CNTFET technology which provides improved energy performance at nanoscale dimensions.  

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