FPGA IMPLEMENTATION OF THE ADVANCED ENCRYPTION STANDARD ALOGRITHM USING VERILOG-HDL

AES (Advanced Encryption Standard) is a secure and efficient symmetric key encryption algorithm widely used for protecting digital information. It operates on 128-bit data blocks and uses secret keys of 128, 192, or 256 bits for encryption and decryption. In this project, the AES encryption algorithm was implemented and analyzed using Verilog HDL. The main operations of AES such as SubBytes, ShiftRows, MixColumns, and AddRoundKey were designed and simulated successfully. SubBytes provides substitution using an S-box, ShiftRows performs cyclic shifting of rows, MixColumns increases diffusion through matrix multiplication, and AddRoundKey combines the data with the round key using XOR operation.The simulation waveforms confirmed the correct functionality of each module. The project provided a clear understanding of cryptographic techniques, digital hardware implementation, and functional verification using simulation tools.

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