MITIGATION OF CRITICAL DELAY IN CARRY SKIP ADDERS USING FinFET 18nm TECHNOLOGY

This paper presented a carry skip adder based on a 10-transistor FinFET full adder in 18 nm technology. The full adder generates the sum with two XNOR gates and the carry with a multiplexer, which removes the AOI stage from the carry path and reduces the critical delay. The cell uses fewer transistors than the CMOS, pass-transistor, transmission-gate and GDI adders reviewed here. Simulation of the 8-bit carry skip adder in Vivado confirmed correct sum and carry generation, and the design is suitable for FPGA implementation. Future work will report post-layout power, delay and area figures, and will study the effect of process variation using Monte Carlo analysis. The adder can then be applied in FIR filters and other arithmetic units where low power and high speed are required.

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