RISC-V PROCESSOR WITH INTEGRATED 2-BIT VEDIC MULTIPLIER FOR LOW- POWER MULTIPLY OPERATIONS

his work demonstrated the implementation of a RISC-V processor integrated with a 2-bit Vedic multiplier for efficient and low-energy multiplication operations. By using the Urdhva Tiryakbhyam Vedic multiplication technique, the processor achieved faster arithmetic computation with reduced delay and improved performance compared to conventional multiplication methods. The proposed design successfully demonstrated the advantages of combining the simplicity and flexibility of the RISC-V architecture with the high-speed capability of Vedic mathematics. Simulation and analysis showed improvements in power efficiency, processing speed, and hardware utilization, making the system suitable for modern embedded and digital signal processing applications. Overall, the project highlights the potential of Vedic multiplier-based processor design in developing compact, energy-efficient, and high-performance computing systems for future real time applications.  

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