Si-ring quantum-well GAA nanowire FET for 5nm CMOS integration

Short-channel effects are a series of phenomena that take place when the channel length of the MOSFET becomes approximately equal to the space charge regions of source and drain junctions with the substrate. They lead to a series of issues including polysilicon gate depletion effect, threshold voltage rolloff, drain- induced barrier lowering (DIBL), velocity saturation, reverse leakage current rise, mobility reduction, hot carrier effects, and similar other annoyances in 5nm scale of transistor. So, to overcome the short- channel effects, gate leakage, and increased variability various methods have been proposed in order to improve the performance of these devices, including the use of materials with high carrier mobility such as germanium or III–V materials, multi gate transistors, tunneling FET (TFET) structures, and structure quantum wells, any of which can significantly reduce SCE (short channel effect).In this paper Si-ring GAA NW FET has proposed due to it has lower static leakage current and a smaller subthreshold slope than conventional MOSFET and GAA, and a good level of electrostatic control is created in the channel due to the channel being surrounded by the cylindrical gate. The performance of the device and its electrical characteristics have been determined using sentaurus TCAD.