FPGA Implementation of Antilogarithmic Computation using Fixed Point Architecture at SoC Integration
DR Prashanth Bachanna, Sunkaraboina Aravind, Ramavath Bhanu Prasad, Praisy Moses
Electronics and Communication Engineering Institute of Aeronautical Engineering Hyderabad, Telangana, India
Abstract—In recent studies works in device system-on-chip (SoC) and Embedded structures applications need optimization of electricity, latency, area, and improvement of throughput. all these packages are complex in operations and to validate FPGA is a high-quality appropriate device with minimal time. maximum of operations in DSP packages uses constant factor and records route are broadly used and attention of complicated arithmetic operations using logarithmic variety systems. so one can improve throughput and optimize electricity, region, and postpone, a novel antilogarithmic architecture has been found on FPGA. The proposed antilogarithmic function uses piecewise linear approximation (PLA), main one detector (LoD), barrel shifter (BS) and Reconfigurable residue variety system (RRNS), Parallel Prefix Adder (PPA) is included in the design. The SoC stage layout has been synthesized in Vivado Design Suite 2018.1 and tested on Artix-7 FPGA. The device utilization demonstrates how little FPGA aid the architecture uses. moreover, we have tested the approximation result through mistake analysis. in line with the mistake looked at, there may be a 2.4 percent. mistake for negative numbers and a zero.24 percentage errors for tremendous values. by the usage of greater bits for the fractional bit illustration, the inaccuracy may be reduced even greater. tool. The tool utilization demonstrates the greatest latency and minimum good judgment sources, and the same design is tested at the FPGA. additionally, we’ve got examined the approximation result via mistake, analysis. The LOD designs and an approximation adder for summing logarithms can be applied to beautify the Mitchell logarithmic (ML) multiplier’s hardware performance. In contrast to the authentic Mitchell multiplier, this layout lowers hardware charges by way of 21 percent.eight, while in contrast to the alternative present-day generation, it lowers fees using 17.5 percentage.
Index Terms—Antilogarithm; fixed-point architecture, leading one detector, approximate adder, Mitchell logarithmic multiplier and FPGA.
