Design and Implementation of Max-Max Pooling Layer Through ASIC for CNN Applications

Pooling layers, especially max pooling, are vital in deep learning architectures for reducing spatial dimensions and preserving salient features. This work proposes a custom ASIC- based hardware architecture for a max-max pooling layer, de- signed to improve the performance and efficiency of convolutional neural networks (CNNs) in resource-constrained environments. The design is implemented in SystemVerilog and validated through comprehensive testbench simulations. It employs a two- stage hierarchical max pooling operation using multiplexers, D flip-flops, and comparators. The core logic supports multiple operational modes via a 2-bit select line, enabling direct input loading, incremental/decremental updates, and default override functionality. A comparator module evaluates threshold condi- tions in real time, enhancing decision-making within the pooling logic. The design ensures minimal latency and synchronous operation with a clocked control system, optimizing hardware utilization. Simulation results confirm functional correctness and demonstrate the feasibility of deploying this architecture in ASIC- based real-time AI applications, such as edge computing and embedded vision systems.