Developing a Multi-Threaded RISC-V Processor for Real-Time Processing Applications
GAJA CHANDANA SRI
Department of ECE Institute of Aeronautical Engineering
Telangana, India 21951A0438@iare.ac.in 0009-0006-2797-3517
MANDULA SRAVANA SREE
Department of ECE Institute of Aeronautical Engineering
Telangana, India 21951A0438@iare.ac.in 0009-0004-0832-8155
VAKKAPATLA VAMSI
Department of ECE Institute of Aeronautical Engineering
Telangana, India 21951A04P8@iare.ac.in 0009-0008-9480-1736
MRS. M. SREEVANI
Assistant Professor Department of ECE
Institute of Aeronautical Engineering Telangana, India m.sreevani@iare.ac.in
Abstract:
The popularity of RISC-V has been growing despite its intrinsic inability to support multithreaded mode. Hence, there have been research efforts toward the development and implementation of multithreaded RISC-V processors. This paper describes a multithreaded Reduced Instruction Set Computer (RISC) processor for improved performance and increased operation speed. It can execute a larger number of instructions with a simple design and lower critical path delay. RISC architecture allows dynamic control of threads with create, execution, halt, delete, etc., operations to reflect the operation of a real-time operating system task queue. We add specific instructions on the top of RISC-V to support these thread control operations. That leads us to the implementation of a multithreaded RISC-V processor with prioritized execution of programs across eight threads and concurrent execution of instructions execution beyond the number of its cores. This capability enables the processor to execute the number of threads greater than its number of cores in parallel. In order to be flexible, scalable, and also low-cost, this design leverages the open-source RISC-V instruction set architecture (ISA) for a wide range of hard-real-time applications, from industrial automation to utonomous systems. The anticipated real-time performance along with the function of the proposed multithreaded RISC-V processor is, showing significant improvements in throughput as well as latency, making it a sturdy solution for the dynamic demands of modern real-time systems.
Keywords: RISC, ISA, Inclusive Creation, Context Switching, Strict Timing.
