Implementation Of N-Bit MAC Unit Using Vedic Multiplier

This paper presents the design and implementation of the N-bit Mac unit using Vedic Multiplier architecture which is developed using the cadence tool. The work reflects the process of implementing the N-bit Vedic Multiplier based on the Urdhva Tiryagbhyam Sutra (Vertically and Crosswise) from the ancient mathematics which significantly offers the advantage of computational speed and resource utilization compared to the conventional multipliers. This also includes the involvement of the ripple carry adder (RCA) and the accumulator unit with the D-Flip Flops for the complete architecture flow. The proposed design conforms a noticeable reduction in the power consumption and area occupation with a less hardware complexity that ensures an increase in the speed of the design. The design is modelled at the transistor level CMOS 180nm technology and the functional verification is done using the Transient analysis in the Cadence Virtuoso Tool. In today’s modern Digital Signal Processing the MAC unit plays a vital role in achieving high speed arithmetic problems and applications. These findings show that use of Vedic Mathematics in VLSI arithmetic operations can significantly improve performance, suggesting it to be a strong option for future DSP system development.