POWER EFFICIENT MODIFIED FIFO BASED HASH JOIN ARCHITECTURE

Abstact- The main objective of this concept is to design a hash join operator with at-most efficiency. This project presents a non-collision parallel static random-access memory (SRAM)-based hash join architecture. This architecture utilizes multiple hash functions and content addressable memories (CAMs) to eliminate hash collision, thereby ensuring a worst constant memory access for each phase in the hash join algorithm and consequently improving the hash join throughput. These Hash joins are useful in the implementation of a relational database management system, sorting, aggregation. In the era of Internet of Things (IOT) and Big Data, fast query processing is a crucial requirement of the modern DBMS. The performance of the central processing unit (CPU) is not growing sufficiently quickly to handle the rapidly increasing amount of data, leading to demands for new processing methods to speed up database systems. A non-collision parallel hash join strategy is proposed. Proposed strategy addresses the hash collision and provides insert and query operations of the hash join algorithm with a worst-case constant time. A parallel hash join architecture comprising multiple channels and a CAM is constructed. This architecture distributes the tuples in different hash channels and therefore, there is no need for duplicate storages. clock gating architecture to limit the switching activity of the address decoder which improves the power efficiency of the proposed FIFO. Element structure is adapted to evaluate the clock cycle to the present ring counter block and to release the clock pulse to the next ring counter block. FIFO Memory accessing does not need write operations so data lines and read/write lines to the SRAM memory architecture is omitted. Index Terms— Database operation, hash join, hardware acceleration, FPGA, parallel pipeline.