Design of Advanced Encryption Standard Using Verilog HDL

Design of Advanced Encryption Standard Using

Verilog HDL

Thipparthi Pooja
dept. ECE

Institute of Aeronautical Engineering Hyderabad, Telangana, India poojareddy0698@gmail.com

Chelle Radhika
dept. ECE

Institute of Aeronautical Engineering Hyderabad, Telangana, India radhikachelle@gmail.com

T. Spandana
dept. ECE

Institute of Aeronautical Engineering Hyderabad, Telangana, India spandana.thupalli@gmail.com

Dandu Maniteja
dept. ECE

Insitute of Aeronautical Engineering Hyderabad, Telangana, India manitejadandu6@gmail.com

Abstract—Cryptography focuses on ensuring the security and integrity of data. Initially, various algorithms were developed for encoding and decoding, but many proved inadequate for protecting large and sensitive datasets. This led to the creation of AES, a robust standard for data encryption and decryption. Originally designed to safeguard highly confidential information, AES has since been adopted widely in networking applications to secure data. It primarily aims to protect sensitive information and is also utilized in network backends to bolster security. AES operates with 16-byte blocks and supports key sizes ranging from 128 to 256 bits. The choice of Verilog over standard VHDL is due to its reduced operational time and lower propagation delays in data encoding and decoding compared to other hardware description languages. Before AES, DES served as the encryption standard, but its limitation of a fixed 56-bit key size posed significant security risks. AES addresses this issue by allowing variable key sizes for enhanced flexibility.

Index Terms—Advanced Encryption Standard, Input text, Cipher text, Verilog.