AES Using Linear Feedback Shift Register (LFSR) for Enhanced Cryptographic Performance
K Kavitha¹, Patan Mohammad Khan², Gandla Likith Kumar³, Vadlamudi Gowtham⁴, Aradyula Bala Murali Krishna⁵
¹Guide of the project, Assistant professor, Department of Electronics and Communication Engineering, Krishna University College of Engineering and Technology, Machilipatnam-521001, India
²,³,⁴,⁵Department of Electronics and Communication Engineering, Krishna University College of Engineering and Technology, Machilipatnam-521001, India
Abstract
AES Using LFSR (Linear Feedback Shift Register) is an approach that integrates the AES encryption algorithm with the use of LFSR-based techniques to enhance the performance, security, and hardware efficiency of the cryptographic system. AES (Advanced Encryption Standard) is one of the most widely used symmetric-key encryption algorithms, offering high security and fast encryption. However, the need for efficient hardware implementations has led to the exploration of various methods to speed up the encryption process while maintaining security.
The integration of LFSR into the AES structure primarily targets the generation of pseudo-random key streams for key expansion or stream cipher generation, improving the randomness and speed of the key schedule, which is a vital part of the AES algorithm. By utilizing LFSR-based key generation techniques, the AES cipher can achieve faster processing speeds, lower hardware complexity, and reduced power consumption in embedded systems, FPGA, and ASIC implementations.
This method focuses on optimizing the AES algorithm's key expansion process by replacing traditional methods with LFSR-based key generation, enhancing the overall throughput while maintaining the encryption strength. The use of LFSR also provides a more flexible and scalable approach, allowing for higher-speed cryptographic operations in hardware implementations.
In this paper, we present the design and implementation of an AES encryption system using LFSR-based key generation and compare it with conventional AES implementations in terms of performance, area efficiency, and power consumption. Experimental results demonstrate that this LFSR-enhanced AES approach significantly improves the throughput, making it suitable for high-performance and resource-constrained environments, particularly in IoT devices, mobile platforms, and real-time cryptographic applications.
Keywords: AES, LFSR, Cryptography, FPGA, Key Expansion, Hardware Security, Verilog.
