2:1 Multiplexer, 1:2 De-multiplexer,2:4 Decoder and 4:2 Encoder Circuit Design with CMOS Technology Implementing with Artificial Neural Network with Verilog HDL Code for Output

2:1 Multiplexer, 1:2 De-multiplexer,2:4 Decoder and 4:2 Encoder Circuit Design with CMOS Technology Implementing with Artificial Neural Network with Verilog HDL Code for Output

Rupam Sardar

Budge Budge Institute of Technology, Kolkata-700137

Abstract:

The goal of this project is to create a De-multiplexer gate using a complementary metal oxide semiconductor (CMOS) and an artificial neural network.When designing any COMS circuit, we always keep in mind that the lowest possible cost should be the aim.In this work, the circuit was designed using a multilayer artificial neural network. We utilize weights to alter the value and treat negative values as inverters and neurons as transistors in our work.We are also developing Verilog-HdL code to easily apply the De-multiplexer for experimenting with an artificial neural network and set weights to acquire the desired results.

The purpose of this project is to use an artificial neural network and a complementary metal oxide semiconductor (CMOS) to develop a decoder gate.We constantly keep in mind that the goal should be to construct a COMS circuit at the lowest feasible cost.An artificial neural network with multiple layers was used to create the circuit in this work. In our study, we treat negative values as inverters and neurons as transistors, and we modify the value using weights.Additionally, we are creating Verilog-HdL code that will make it simple to use the Decoder to experiment with artificial neural networks and adjust weights to get the desired outcomes.

The purpose of this project is to use an artificial neural network and a complementary metal oxide semiconductor (CMOS) to develop a decoder gate.We constantly keep in mind that the goal should be to construct a COMS circuit at the lowest feasible cost.An artificial neural network with multiple layers was used to create the circuit in this work. In our study, we treat negative values as inverters and neurons as transistors, and we modify the value using weights.Additionally, we are creating Verilog-HdL code that will make it simple to use the Decoder to experiment with artificial neural networks and adjust weights to get the desired outcomes. The purpose of this research is to use an artificial neural network and a complementary metal oxide semiconductor (CMOS) to produce a multiplexer  gate.We always keep in mind that the lowest feasible cost should be the goal while designing any COMS circuit.This work used a multilayer artificial neural network to design the circuit. In our work, we treat neurons as transistors and negative values as inverters, and we use weights to adjust the value.In order to effortlessly apply the Multiplexer for experimenting with an artificial neural network and set weights to obtain the desired results, we are also building Verilog-HdL code.Keywords: Multiplexer, CMOS,ANN,Verilog-HDL.

.Keywords: Multiplexer De-multiplexer, Decoder, Encoder Verilog-HDL, CMOS, ANN, Verilog HDL