A 45nm AND 65nm CMOS IMPLEMENTATION OF 12T SRAM CELL WITH SOFT ERROR READ STABILITY OF MULTINODE UPSET RECOVERABILITY FOR AEROSPACE APPLICATION

A 45nm AND 65nm CMOS IMPLEMENTATION OF 12T SRAM CELL WITH SOFT ERROR READ STABILITY OF MULTINODE UPSET RECOVERABILITY FOR AEROSPACE APPLICATION

Keerthana T1, Ramya R S2

PG Student1, Associate Proessor2

Department of VLSI, AVS Engineering College, Salem.

keerthanat045@gmail.com, ramyaselvaraju@gmail.com

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Abstract – With technology advancing rapidly, the size of transistors and the distance between them is decreasing quickly. This reduction in size is causing the critical charge of sensitive nodes in SRAM cells to decrease, making them more susceptible to soft errors, especially in aerospace applications. When a radiation particle strikes a open node in a standard 6T SRAM cell, the storage data in the cell can be changed, leading to a single-event upset (SEU). To address this issue, a new Soft Error Read and write Stability improves Low Power 12T (SARP12T) SRAM cell has been introduced in this study to reduce the impact of SEUs. The performance of SARP12T has been compared to other recently developed soft-error-aware SRAM cells like QUCCE12T, QUATRO12T, RHD12T, RHPD12T, and RSP14T. SARP12T is designed for the recoverability of all stored data in sensitive nodes even if they are affected by radiation strikes. Additionally, SARP12T can overcome single-event multi-node upsets (SEMNUs) that may happened at its sensitive node pair. This proposed cell also boasts the higher read stability, as the storage node holding '0' can regain from any upset during read operations. Moreover, SARP12T consumes the minimum amount of hold power, has greater write ability, and lower write delay compared to other similar cells. Despite a almost greater read delay and higher read and write energy consumption, the improvements in the proposed SARP12T cell make it a promising solution for mitigating soft errors in SRAM cells.