A Low-Power DNN Accelerator With Mean- Error-Minimized Approximate Signed Multiplier

A Low-Power DNN Accelerator With Mean- Error-Minimized Approximate Signed Multiplier

 

 

      Dinesh S

Department Of Electronics and

Communication Engineering

Panimalar Institute Of Technology

Chennai, India

        pksdinesh705@gmail.com

 

Deveshkumar R                                                  Arunthavaraj A

Department Of Electronics and                          Department Of Electronics and

   Communication Engineering                            Communication Engineering

Panimalar Institute Of Technology                   Panimalar Institute Of Technology

            Chennai, India                                                 Chennai, India

 deveshramesh670@gmail.com                            arunthavaraj935@gmail.com

 

 

 

Dr. D. Arul Kumar, M.E., Ph.D.

          Associate Professor

 Department Of Electronics and

     Communication Engineering

Panimalar Institute Of Technology

Chennai, India

 

Dr. S. Sathiya Priya, M.E., Ph.D.                            Dr. V. Jeya Ramya, M.E., Ph.D.

          Professor & HOD                                            Associate Professor

Department Of Electronics and                          Department Of Electronics and

   Communication Engineering                            Communication Engineering

Panimalar Institute Of Technology                   Panimalar Institute Of Technology

            Chennai, India                                                 Chennai, India

  priya.anbunathan@gmail.com                             jeyaramyav@gmail.com

 

 

 

Abstract— The offloading of artificial intelligence workloads onto edge devices has created escalating demand for energy-efficient hardware accelerators that offer high-throughput deep neural network (DNN) inference with acceptable accuracy. In this paper, we present a novel low-power DNN accelerator architecture with a Mean-Error-Minimized Approximate Signed Multiplier (MEMASM) that is designed to minimize energy consumed on signed multiplication operations — one of the primary sources of computational complexity in DNNs. The MEMASM applies approximate computation techniques to compromise minimal accuracy for significant power and area savings. In contrast to traditional approximate multipliers, which tend to overlook sign handling and build up huge errors, MEMASM is designed to minimize the mean error distance (MED) while preserving correct sign representation. This guarantees the functional correctness of signed multiplications in approximate computation. Our design incorporates MEMASM blocks into the multiply-and-accumulate (MAC) blocks of a systolic-based DNN accelerator. For performance analysis, we fabricated the design with a 45nm CMOS process and verified it on benchmark neural network models, including LeNet and VGG models. The outcome reveals that our design has up to X% reduced power consumption and Y% area overhead reduction as opposed to exact multipliers while maintaining inference accuracy within Z% of the baseline. In addition, we also compared with

existing approximate multipliers and demonstrated the efficiency of MEMASM in achieving an improved energy efficiency-accuracy trade-off. The technique provides scalable deployment of DNNs on power-limited edge devices such as IoT nodes, wearables, and smartphones. This paper demonstrates that hardware-based approximate arithmetic, if optimally optimized, can leapfrog significantly in the field of low-power AI acceleration.

Keywords—Deep Neural Network (DNN), Low-Power Design, Hardware Accelerator, Mean Error Distance (MED), Approximate Computing, Approximate Multiplier