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A Low-Power High-Accuracy Approximate Multiplier Using High-Order Approximate Compressors
A Low-Power High-Accuracy Approximate Multiplier Using High-Order Approximate Compressors
Banoth Ashwini
Electronics and Communication Engineering Institute of Aeronautical Engineering Hyderabad, Telangana, India banothashwini9980@gmail.com
Vyasa Ranjith Kumar
Electronics and Communication Engineering Institute of Aeronautical Engineering Hyderabad, Telangana, India ranjithkumarvyasa@gmail.com
Nallawar Amulya
Electronics and Communication Engineering Institute of Aeronautical Engineering Hyderabad, Telangana, India nallawaramulya@gmail.com
Dr.P.Munaswamy, Professor and Head
Electronics and Communication Engineering Institute of Aeronautical Engineering Hyderabad, Telangana, India p.munaswamy@iare.ac.in
Abstract—To address the need to reduce power consumption, approximate multipliers have emerged as a potential solution for fault-tolerant applications. In this work, we present a new 8x8 approximate multiplier that focuses on minimizing performance while maintaining a high degree of accuracy. The design features two key features: firstly, based on their importance, different weights are handled by the compressors with different levels of precision, allowing for a trade-off between energy efficiency and minimum error. Second, higher order approximation compressors such as 8:2 compressors are used for intermediate weights to simplify the drive chain logic. This is, to our knowledge, the first design to successfully integrate higher-order approximate compressors into an approximate multiplier. Compared to a precision multiplier such as the Dadda tree multiplier, experimental results show that the proposed design offers significant energy savings while maintaining high accuracy.
Key Words:- Approximate computing; Arithmetic circuits; Logic design; Low-power design; Partial Product reduction
