Design And Implementation of Pattern Latching Algorithm for MCU Performance Analysis Using Ring Oscillator
Deepak Prasanna B
Department Of Electronics and Communication,
Panimalar Institute Of Technology, Chennai
, India deepakprasanna1312@gmail.com
Nagenthira Kumar D
Department Of Electronics and Communication,
Panimalar Institute Of Technology, Chennai,
India nagenthirakumar1204@gmail.com
Lokesh N S
Department Of Electronics and Communication,
Panimalar Institute Of Technology, Chennai,
India srinivasanlokesh44@gmail.com
Dr. V Jeyaramya, M.E,Ph.D
Assistant Professor Department Of Electronics and Communication
Panimalar Institute Of Technology Chennai,
India jeyaramyavv@gmail.com
Abstract— The testing of integrated circuits, particularly in safety-critical applications such as the automotive industry, holds paramount importance to ensure the reliability and functionality of microcontrollers (MCUs). In safety-critical systems within vehicles, MCUs play a pivotal role in controlling various functions, ranging from engine management to advanced driver assistance systems. One of the critical tests in the assessment of MCU performance is the performance screening, where the maximum clock frequency of the MCU is determined. The clock frequency of an MCU signifies the rate at which the device processes instructions and performs operations. In safety- critical automotive applications, precision and reliability are non-negotiable, as the MCU's ability to execute instructions promptly directly impacts the overall performance of electronic control units (ECUs). The performance screening process involves subjecting the MCU to varying clock frequencies to identify its maximum operational limit. This test is essential for ensuring that the MCU can meet the stringent performance requirements demanded by safety-critical automotive systems. In the existing system, performance analysis using ring oscillator method is implemented. In the proposed system pattern analysis of configurable ring oscillator is implemented using pattern latching algorithm. A clocked latch with synchronous gate is utilized to correlate the ring oscillator circuits. The proposed model is applied with digital delay locked loop (DDLL) circuit to ensure the changes occurring in the MCU performance measure.
Keywords— Microcontroller Performance, Configurable Ring Oscillator (CRO), Pattern Latching Algorithm (PLA), Digital Delay-Locked Loop (DDLL), Accuracy Improvement, Jitter Reduction, Fault Detection, Power Optimization, Real-Time Monitoring, Embedded Systems, Scalability, Security.
