Design and Performance Analysis of an 8-Bit Approximate Multiplier Using Single Exact Single Approximate Adders and Single Exact Dual Approximate Adders

Adders form the core arithmetic building blocks in digital Very Large Scale Integration (VLSI) systems. In recent years, approximate adder designs have gained significant attention as an effective approach to optimize key performance metrics such as power consumption, delay, and hardware complexity. Similarly, digital multipliers are essential components in many digital signal processing (DSP) applications and typically dominate the overall computational cost. Since a wide range of DSP applications can tolerate a certain degree of computational inaccuracy, approximate multiplication emerges as a viable solution to achieve favorable trade-offs among energy efficiency, performance, and accuracy, particularly in energy-constrained computing environments. Additionally, supply voltage scaling has been demonstrated as an efficient technique to further reduce total energy consumption. In this work, a multiplexer-based approximate full adder is introduced and employed in the design of an 8-bit approximate multiplier. The proposed circuit architecture enables error-resilient multiplication while operating at a reduced supply voltage. Simulation results demonstrate that the proposed 8-bit approximate multiplier achieves the lowest energy consumption per operation while maintaining comparable computational accuracy relative to existing multiplier designs for 8-bit operands. Furthermore, the proposed design achieves a 26.7% reduction in energy–delay product (EDP) when compared with conventional exact multiplication architectures.