Design and Performance Analysis of Low Power 6T SRAM Cell in 45nm CMOS Technology

Design and Performance Analysis of Low Power 6T SRAM Cell in 45nm CMOS Technology

 Paramandla Akhila1 Dept of ECE IARE

Dr. S China Venkateshwarlu2 Professor Dept of ECE IARE

Dr. V Siva Nagaraju3 Professor Dept of ECE IARE

 Ms. P Ganga Bhavani4 Assist. Professor Dept of ECE IARE

Abstract - This project presents the design and analysis of a low power 6-transistor (6T) SRAM cell using 45nm CMOS technology. SRAM is an important memory used in processors and embedded systems. With technology scaling to 45nm, reducing power consumption and delay is essential, especially for battery-operated devices. The 6T SRAM cell is designed and simulated in Cadence Virtuoso at a 1V supply voltage. Key parameters like read/write power and delay are evaluated. The design is verified using DRC and LVS to ensure accuracy. Results show that the 6T SRAM cell provides low read power and good performance, making it suitable for low power applications in modern electronic devices.

Key Words : AES Encryption, FPGA Implementation, Side-Channel Leakage, Vivado Design Suite, Power Analysis Attacks, Electromagnetic Analysis, Timing Attacks, Hardware Security, Cryptographic Countermeasures, Masking Techniques, S-box Protection, Clock Jittering, Noise Insertion, High-Level Synthesis (HLS), IP Integrator, Floor planning, Resource Utilization, Performance Optimization, RTL Design, Secure FPGA Design.