Design of Area and Power Efficient Digital FIR filter for FPGA

This paper presents the design and implementation of an area and power-efficient Digital Finite Impulse Response (FIR) filter optimized for FPGA platforms. The proposed architecture focuses on minimizing resource utilization and dynamic power consumption while maintaining high performance. A 4-tap FIR filter is developed using a multiplexer-based adder to reduce logic complexity and a Radix-8 Booth multiplier to improve multiplication efficiency. This combination effectively decreases the number of logic elements and switching activity, leading to enhanced power and area efficiency. The design is synthesized and implemented on an FPGA, and key performance parameters such as LUT usage, power consumption, and timing analysis are evaluated. Simulation and synthesis results confirm the effectiveness of the proposed architecture for low-power, high-performance digital signal processing applications.