Design of Area and Power Efficient Digital FIR filter for FPGA
Udhayanidhi M
Department Of Electronics and Communication Engineering Panimalar Institute Of Technology Chennai, India udhayanidhimaruthamuthu@gmail.com
Sandosh Kumar R
Department Of Electronics and Communication Engineering Panimalar Institute Of Technology Chennai, India sandoshkumar790455@gmail.com
Sivaneshwaran J
Department Of Electronics and Communication Engineering Panimalar Institute Of Technology Chennai, India sivaneshwaranj@gmail.com
Mr. D. Gurupandi M.E.,
Assistant Professor
Department Of Electronics and Communication Engineering Panimalar Institute Of Technology Chennai, India gurupandi85@gmail.com
Dr. S. Sathiya Priya M.E., Ph.D.,
Professor & HOD
Department Of Electronics and Communication Engineering Panimalar Institute Of Technology Chennai, India priya.anbunathan@gmail.com
Dr. V. JeyaRamya M.E., Ph.D.,
Associate Professor
Department Of Electronics and Communication Engineering Panimalar Institute Of Technology Chennai, India jeyaramyav@gmail.com
Abstract— This paper presents the design and implementation of an area and power-efficient Digital Finite Impulse Response (FIR) filter optimized for FPGA platforms. The proposed architecture focuses on minimizing resource utilization and dynamic power consumption while maintaining high performance. A 4-tap FIR filter is developed using a multiplexer-based adder to reduce logic complexity and a Radix-8 Booth multiplier to improve multiplication efficiency. This combination effectively decreases the number of logic elements and switching activity, leading to enhanced power and area efficiency. The design is synthesized and implemented on an FPGA, and key performance parameters such as LUT usage, power consumption, and timing analysis are evaluated. Simulation and synthesis results confirm the effectiveness of the proposed architecture for low-power, high-performance digital signal processing applications.
Keywords— FIR filter, FPGA implementation, low power design, area efficiency, Radix-8 Booth multiplier, multiplexer-based adder, digital signal processing, hardware optimization.
