Design of Three Stage Dynamic Comparator with Tail Transistor using 20nm FinFET Technology for ADCs

Design of Three Stage Dynamic Comparator with Tail Transistor using 20nm FinFET Technology for ADCs

Monalisa chatterjee1, Ravish Gupta2

1 Research Scholar, Department of Electronics & Communication, Dr. CV Raman University, Kota, Bilaspur, Chhattisgarh, India

2 Asst. Professor, Department of Electronics & Communication, Dr. CV Raman University, Kota, Bilaspur, Chhattisgarh, India

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Abstract— According to this article, one of the key disadvantages is excessive power consumption and offset in CMOS based comparators. At scale down technology, CMOS suffers with short channel effect and leakage current. To address these challenges, FinFET technology is used in threestage dynamic comparators instead of traditional circuit designs. The energy efficiency of FinFET-based dynamic comparators is higher than that of CMOS, and the short channel effect and leakage current are decreased. Furthermore, a new design of FinFET-based three stage dynamic comparators with tail transistors was created and simulated using the cadence virtuoso environment. In comparison to three-stage dynamic comparators without tail transistors, the three-stage dynamic comparator with tail transistor in this approach decreases offset, power consumption, and energy consumption. Both the standard three stage dynamic comparators without tail transistor and the modified three stage dynamic comparators with tail transistor are implemented in the same 20nm FinFET technology for easy comparison. According to simulation results, the modified three stage comparator decreases power consumption by 20% it has a 17% energy efficiency.

Keywords— CMOS, FinFET, Dynamic comparators, Input referred noise, Power Consumption, Tail transistor.