High-Performance AES Encryption Architecture on FPGA Using Pipelined Simulation and Adaptive NoC Routing

High-Performance AES Encryption Architecture on FPGA Using Pipelined Simulation and Adaptive NoC Routing

Ballu Manikanta1 Dept of ECE IARE

Dr. S China Venkateshwarlu2 Professor Dept of ECE IARE

Dr. V Siva Nagaraju3 Professor Dept of ECE IARE

Ms. P Ganga Bhavani4 Assist. Professor Dept of ECE IARE

Abstract - Optimization of reconfigurable multicore processors through pipelining of cryptographic modules offers significant improvements in both performance and security. This work presents a design and implementation of pipelined AES and SHA modules on an FPGA platform to enhance throughput and reduce power consumption in a multicore processor architecture. Simulation results using ModelSim demonstrate that the pipelined approach increases the number of processed packets per second and decreases latency compared to existing baseline designs. Additionally, power analysis shows reduced energy usage without compromising cryptographic strength. The proposed design achieves a balanced trade-off between speed, security, and resource utilization, making it suitable for secure high-speed applications.

Key Words : AES Encryption, SHA Hashing, FPGA Implementation, Pipelining, Reconfigurable Multicore Processor, Hardware Security, Power Optimization, Performance Enhancement, Cryptographic Accelerator, ModelSim Simulation, Resource Utilization, Low-Power Design, Throughput Improvement, RTL Design, Vivado Design Suite, Secure Hardware Architecture, Timing Analysis, Power Consumption, Packet Processing, Dynamic Routing.