Low Transition Clock Gated Timing Error Detection and Correction in Digital Circuits

Low Transition Clock Gated Timing Error Detection and Correction in Digital Circuits

Krithik Kanvar N

Department Of Electronics and

Communication Engineering

Panimalar Institute Of Technology

Chennai, India

krithkkanvar@gmail.com

Gokulavasan S                                                                Gowtham R G

Department Of Electronics and                           Department Of Electronics and

Communication Engineering                                Communication Engineering

Panimalar Institute Of Technology                   Panimalar Institute Of Technology

                 Chennai, India                                                              Chennai, India

gvasan233@gmail.com                                          rggowtham65@gmail.com

Mr. D. Guru Pandi, M.E.

Assistant Professor

Department Of Electronics and

Communication Engineering

Panimalar Institute Of Technology

Chennai, India gurupandi85@gmail.com

Dr. S. Sathiya Priya, M.E., Ph.D.                            Dr. V. Jeya Ramya, M.E., Ph.D.

Professor & HOD                                                        Associate Professor

Department Of Electronics and                           Department Of Electronics and

Communication Engineering                                Communication Engineering

Panimalar Institute Of Technology                   Panimalar Institute Of Technology

                 Chennai, India                                                         Chennai, India

priya.anbunathan@gmail.com                                 jeyaramyav@gmail.com

      Abstract— Timing error is now getting increased attention due to the high rate of error-occurrence on semiconductors. Even slight external disturbance can threaten the timing margin between successive clocks since the latest semiconductor operates with high frequency and small supply voltage. To deal with a timing error, many techniques have been introduced. Nevertheless, existing methods that mitigate a timing error mostly have time-delaying mechanisms and too complex operation, resulting in a timing problem on clock-based systems and hardware overhead. In the proposed work a novel timing-error-tolerant method that can correct a timing error instantly through a simple mechanism is demonstrated. By modifying a clock in a flip-flop, the proposed system can recover a timing error without the loss of time in the clock-based system. Furthermore, in order to reduce power consumption in the stages were operation is not performed. Clock gating mechanism is used to reduce the unwanted transition. Look-Ahead Clock Gating (LACG) computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. It has however a big advantage of avoiding the tight timing constraints of earlier methods, by allotting a full clock cycle for the enabling signals to be computed and propagate to their gates. Due to the compact mechanism, the proposed system has low hardware overhead in comparison with existing timing-error-tolerant systems that can recover the error instantly. To verify our method, the proposed circuit was extensively simulated by addressing PVT variations. Moreover, it was implemented in several benchmark designs, including a microprocessor.

      Keywords— timing error, flip-flop modification, low power design, clock gating, Look-Ahead Clock Gating (LACG), timing-error-tolerant system, PVT variation, hardware optimization, high-frequency circuits, semiconductor reliability