MODIFIED HIGH SPEED AND LOW POWER 32-BIT VEDIC MULTIPLIER DESIGN AND IMPLEMENTATION

The multiplier speed is a significant feature as the multiplier forms an important part of many systems like FIR filters, microprocessors, DSPs etc. The multiplier is slow as compared to other parts of the system hence it is the speed determining factor of the system. An improvement in speed of the multiplier leads to an improvement in speed of the overall speed. The multiplier speed not only depends on the multiplication technique used it is also depends on the type of adder employed for the addition of the partial products. The proposedhigh speed and low power 32-bit Vedic multiplier architectures based on Vedic sutra namely, Urdhva-Triyag using Carry Save Adder(CSA) has been implemented.Among various methods of multiplication, recently Vedic multipliers are being more efficient. These sutras meant for fastercalculation.Urdhva-Triyag is more efficient than other multipliers with respect to speed. The most significant aspect of the Urdhva-Triyag sutra is, the developed multiplier generates allpartial products in one step. High speed adders are used in the architecture instead of conventional Ripple carry adders thereby reducing the delay further.Finally, the results are comparedwith conventional multipliers to show the efficiency in terms of speed.The effectiveness of theproposed method is synthesized and simulated using Xilinx tool using Verilog coding Software Tools: · Xilinx ISE 14.7 Tool