Power Optimization in VLSI Circuits: A Comparative Study of Flip-Flop Architectures with NOR Clock Gating

Power Optimization in VLSI Circuits: A Comparative Study of Flip-Flop Architectures with NOR Clock Gating

Paramita Chowdhury1, Sunipa Roy2*, Aparajita Datta Sinha3, Molla Safidur Rahaman4 , Ankit Mahata5, Anshu Das6, Arnesh Halder7
1,3,4,5,6,7 Departmentof Electronics and Communication Engineering, Netaji Subhash Engineering College, Techno City, Garia, Kolkata: 700152

*2 Department of Electronics and Communication Engineering, Gurunanak Institute of Technology, Panihati, Kolkata: 700114

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Abstract - Power efficiency has become a paramount concern in modern VLSI circuits, particularly for low-power applica tions. Flip-flops and clock distribution networks (CDNs) contribute significantly to dynamic power consumption, thus heavily impactingsystem performance. This paper proposes a novel Pulse-Triggered Flip-Flop (P-FF) architecture that incorporates an advanced pulse control mechanism combined with a NOR-based clock gating technique to address power inefficiencies. The proposed design minimizes the number of stacked NMOS transistors, employs conditional pulse enhancement during critical transitions, and strategically gates the clock to reduce unnecessary switching activity. Simulations conducted using Tanner EDA tools at a 250 nm CMOS technology node across a wide input voltage range (-1V to 5V) demonstrate that the proposed flip-flop achieves up to 89% reduction in power consumption compared to conventional flip-flop designs such as MHLFF, IMFF, and SECCER-FF. The results further highlight that the proposed P- FF provides superior dynamic power savings, reduced leaka ge, simplified structure, and robust performance across varying operating conditions. These characteristics make the proposed flip-flop an ideal candidate for next-generation low-power VLSI applications, including portable electronics, embedded systems, and high-performance computing platforms.

Key Words: low power, CMOS, SECCER-FF, EDA, P-FF.