Reconfigurable Computing and FPGAs for Adaptive AI Workloads
Anant Manish Singh
anantsingh1302@gmail.com
Department of Computer Engineering
Thakur College of Engineering and Technology, Mumbai, Maharashtra, India
Divyanshu Brijendra Singh
singhdivyanshu7869@gmail.com
Department of Computer Engineering
Thakur College of Engineering and Technology (TCET), Mumbai, Maharashtra, India
Aditya Ratnesh Pandey
ap7302758@gmail.com
Department of Computer Engineering
Thakur College of Engineering and Technology (TCET), Mumbai, Maharashtra, India
Maroof Rehan Siddiqui
maroof.siddiqui55@gmail.com
Department of Computer Engineering
Thakur College of Engineering and Technology (TCET), Mumbai, Maharashtra, India
Akash Pradeep Sharma
sharmaakash22803@gmail.com
Department of Computer Engineering
Thakur College of Engineering and Technology (TCET), Mumbai, Maharashtra, India
Amaan Zubair Khan
hhkhananamaan@gmail.com
Department of Computer Engineering
Thakur College of Engineering and Technology (TCET), Mumbai, Maharashtra, India
Abstract
Reconfigurable computing using Field-Programmable Gate Arrays (FPGAs) is rapidly emerging as a critical solution for adaptive and efficient AI processing. The ability to dynamically adapt hardware resources to changing AI workloads enables significant gains in energy efficiency, latency and throughput, especially for edge and real-time applications. In this work, we present a novel Dynamically Reconfigurable AI Processor (DRAP) framework that leverages dynamic partial reconfiguration (DPR), hardware-software co-design and multicast-optimized dataflow to address major bottlenecks identified in recent literature. Real-time experiments on Xilinx Virtex-7 and Intel Stratix 10 NX platforms demonstrate up to 12.6× higher TOPS/W efficiency and 38% lower inference latency compared to leading GPU solutions. Our approach achieves 89% logic utilization and a 53.8% reduction in energy consumption for pruned convolutional neural networks (CNNs) in video analytics. We validate our results with industry-relevant workloads and compare DRAP to state-of-the-art methods, showing that our framework mitigates key gaps such as static resource allocation, inefficient multicast handling and thermal bottlenecks. This paper provides a comprehensive analysis of dynamic hardware adaptation strategies for FPGAs offering actionable insights for deploying adaptive AI at scale.
