Single bit fault detecting ALU design using reversible gates

Single bit fault detecting ALU design using reversible gates

Anagandhula Jagadeesh, Athe Ajay, Chinthala Karthik, Mrs A Vinisha

UG Scholars, Assistant Professor

Department of ECE[Electronics and Communication Engineering], Guru Nanak Institutions Technical Campus, Hyderabad, Telangana, India

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Abstract - In this digital world, technology depends on the operations of A.L.U to decide the system performance. The need for an Arithmetic Logic Unit (ALU) is as important as the computer, simply because ALU forms the fundamental part of any Central Processing Unit (CPU). And so the encryption of an ALU is highly mandatory for the safety of the device as there are hardly any device without an ALU .The semiconductor industry has been experiencing a massive upgradation in terms of speed and device performance due to device scaling since the invention of MOSFETs in 1960s, but simultaneously power dissipation has also been a major concern. With the device scaling having reached its limit, researchers are looking for a breakthrough technology. One of the emerging fields in the VLSI industry is Reversible Computing. This technology has largely attracted the researchers, because of zero power dissipation in reversible logic circuits. The proposed work here is towards designing an ALU using reversible quantum gates. The proposed ALU performs both arithmetic and logical operations, either of which can be selected as per the requirement. The design uses Fredkin and CNOT gate, which are parity preserving reversible gates. The proposed design is modelled using Verilog HDL and simulated in XILINX software. The design is focused on reducing the number of gates, quantum cost, Garbage outputs and ancillary inputs or constant inputs.