Verification of High Speed on Chip with VIP using System Verilog

Verification of High Speed on Chip with VIP using System Verilog

Yoddha Shivani Kalpeshkumar1, Prof. Suresh Bharwad2, Er. Bhavinkumar R. Patel3
1 M.E (VLSI Design), School of Electronics and communication, L. D. College of Engineering Campus, Ahmedabad, India.

2 Assistant Professor, School of Electronics and communication, L. D. College of Engineering Campus, Ahmedabad, India.

3 Senior Technical Lead at Einfochips an Arrow company, Ahmedabad, India

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Abstract - The exploration work is addressing verification of High speed on chips protocol; we've used the system Verilog grounded test bench structure. I developed a system Verilog law and vindicating using Synopsys VCS tool & EDA playground (open source). Deployment of a layered test bench verification methodology, combined with the use of constrained random verification techniques, which are required to meet the challenge of verifying a subsystem which uses the AMBA on-chip Bus protocol. The verification of high- speed on- chip personality (Verification IP) protocol using System Verilog is a critical aspect of designing complex systems- on- chip (SoCs) that apply the Advanced extensible Interface (ON-CHIP) protocol. The ON-CHIP protocol is a extensively used interface standard for communication between different functional blocks within an SoC, and it plays a pivotal part in icing effective data transfer and synchronization between these blocks. The verification of the ON-CHIP protocol involves expansive testing of colorful functional scripts, including read and write deals, burst transfers, address and data range transformations, and protocol timing constraints. The verification process requires comprehensive testbench development, encompassing the generation of valid ON-CHIP deals, monitoring of protocol signals, and analysis of responses from the DUT (Design Under Test). Also, functional content analysis, assertion- grounded verification, and formal verification ways are employed to insure complete and robust verification of the ON-CHIP protocol. The challenge in vindicating high- speed on- chip personality protocol lies in the complexity and performance conditions of ultramodern SoCs, which demand effective and rigorous verification methodologies to achieve high quality and dependable designs. likewise, the adding demand for high- speed and low- quiescence communication in advanced SoCs necessitates the verification of ON-CHIP protocol at different timepiece frequentness and data transfer rates, posing fresh challenges in achieving accurate and effective verification. This abstract presents the need for vindicating the high- speed on- chip personality protocol using System Verilog, fastening on the challenges and methodologies involved in achieving comprehensive and dependable verification of the ON-CHIP protocol. It highlights the significance of advanced verification ways and methodologies to ensure error-free operation of the ON-CHIP protocol in complex SoCs, leading to robust and dependable system designs. A directed testing methodology cannot produce enough system stimulants to reach the needed content pretensions in the docked design cycle. Exercise and scalability are another crucial consideration with verification as well as with IP. The verification methodology must support exercise similar that tests at one hierarchical position can be reused at the coming. Position over, as well as with the coming design. With a layered verification approach, lower layers like protocol verification are reused in advanced situations. Also, to meet up with coming generation forthcoming 5G technology by probing on on-chip protocol is largely used to acclimatize reusability in perplexed design verification part. So, at the expansive position this protocol is extensively used in numerous diligences as a connecting block to meet the anticipated and factual labors.

Keywords: Verification-IP, on-chip Protocol, System Verilog, Verification Environment.